DEPARTMENT OF ELECTRONICS AND COMPUTER ENGINEERING

MS. MAHI ITAGI

Designation:Assistant Professor (On Contract)
Qualification:
ME: Digital Electronics – Visvesvaraya Technological University (VTU)
BE: Electronics and Telecommunication – Goa University
Experience :
Teaching -8 years 4 months
Areas of Interest :
Digital CMOS VLSI, Embedded Systems
Email:

mahii1225@gmail.com,mahi@pccegoa.edu.in

8 years & 4 months

  • Working as an Assistant Professor in Padre Conceicao college of Engineering, Verna, Dept. of ETC Engg, on contract basis from 03/02/2014 till date
  • Worked as Lecturer in SDM College of Engineering and Technology, Dharwad, Dept. of ECE, on temporary basis from 24/08/2013 to 31/12/20138

NIL

  • Maintenance and fault finding of Electronic Circuits,1 day,12th June 2018,”Agnel Polytechnic, Verna”
  • “Cadence-Design, Analysis and Simulation of Circuits”,5 days,01/01/2018 to 05/01/2018,”PCCE, Goa”
  • “FDP sponsored by Entrepreneurship Development Institute of India, Govt. of India”,2 weeks,27/06/17 to 07/07/17,”CIBA, Verna”
  • Big Data and Internet Of Things,5 days,09/05/16 to 13/05/16,”PCCE, Verna”
  • Embedded systems on Raspberry Pi,5 days,23rd to 27th June 2014,”PCCE, Verna”
  • Indian Contribution to Digital Technology,1 day,25th November 2013,”SDMCET, Dharwad”
  • Automotive Electronics,1 day,30th December 2011,”SDMCET, Dharwad”
  • Overview of ARM Microcontroller & its applications,1 day,28th September’13,”SDMCET, Dharwad”
  • Advancements in Digital Image Processing and Project Based Teaching-Learning,2 days,22nd and 23rd November 2013,”SDMCET, Dharwad”
  • Model Based Approaches for Signal Processing & Communication Applications,2 days,29th and 30th November 2013,”SDMCET, Dharwad”
  • National Conference on Emerging trends in Engineering and Management,Shivamogga,PES Institute of Technology and Management,Performance Analysis of Viterbi Decoder in AWGN Channel,1st and 2nd March 2013
  • National Conference on Emerging trends in Engineering and Technology,Bangalore,Sapthagiri College of Engineering,Performance Analysis of Single Precision Floating Point Addition using VHDL and IP Core Generator,11th May 2013
  • National Conference on Women in Science and Engineering,Dharwad,”SDMCET, Dharwad”,Design and Simulation of Floating Point Pipelined ALU Using HDL and IP Core Generator,5th and 6th July 2013,ISSN 2277-4106
  • International Journal of Computer Information Systems,,Impact of Quantization Matrix on the Performance of JPEG,2012,”Vol. 5, No. 5″

  • STTP/ Internship, 1 Week, March 2021, PCCE, Verna, Co-ordinator/ Resourse Person

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Life Member of ISTE